Never Forget Syntax: The Ultimate VHDL Cheat Sheet

VHDL Cheat Sheet: The Ultimate Quick Reference Guide VHDL (VHSIC Hardware Description Language) is a powerful tool for designing digital systems. Because its syntax is strict and verbose, having a quick reference guide saves development time. This cheat sheet covers the essential syntax, structures, and code patterns you need for everyday programmable logic design. Basic Structure

Every VHDL file requires three main parts: library declarations, an entity, and an architecture.

– 1. Library Declarations library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; – Use for arithmetic operations – 2. Entity (Defines the interface/pins) entity AndGate is port ( a : in std_logic; b : in std_logic; y : out std_logic ); end entity AndGate; – 3. Architecture (Defines the internal behavior) architecture Behavioral of AndGate is – Internal signals are declared here begin y <= a and b; – Concurrent assignment end architecture Behavioral; Use code with caution. Data Types and Literals

VHDL is a strongly typed language. Types must match precisely during assignment. Common Types

std_logic: Represents a single bit (‘0’, ‘1’, ‘Z’ for high-impedance, ‘X’ for unknown).

std_logic_vector: An array of bits. Example: std_logic_vector(7 downto 0) for an 8-bit bus.

integer: Represents a whole number. Range can be restricted: integer range 0 to 255.

unsigned / signed: Found in NUMERIC_STD. Used for math operations on bit vectors. Syntax Literals Single bit: ‘1’ or ‘0’ (single quotes). Bit vector: “10101010” (double quotes). Hexadecimal: X”FF” (prefix with X, double quotes).

Operators are grouped by precedence, from highest to lowest. Logical: and, or, nand, nor, xor, xnor, not Relational: =, /=, <, <=, >, >= Shift: sll, srl, sla, sra, rol, ror Arithmetic: +, -, *, /, rem, mod Combinational Logic Patterns

Combinational logic changes outputs immediately when inputs change. It does not require a clock. Conditional Signal Assignment (When-Else) mux_out <= input_a when selection = ‘1’ else input_b; Use code with caution. Selected Signal Assignment (With-Select)

with selection select mux_out <= input_a when “00”, input_b when “01”, input_c when “10”, input_d when others; Use code with caution. Sequential Logic Patterns

Sequential logic synchronizes data changes to a clock edge. This requires a process block. Flip-Flop with Asynchronous Reset

process(clk, reset) begin if reset = ‘1’ then q <= ‘0’; elsif rising_edge(clk) then q <= d; end if; end process; Use code with caution. Flip-Flop with Synchronous Reset

process(clk) begin if rising_edge(clk) then if reset = ‘1’ then q <= ‘0’; else q <= d; end if; end if; end process; Use code with caution. Process Statements

Processes isolate sequential logic. Inside a process, statements execute sequentially, but the process itself runs concurrently with the rest of the architecture. If-Then-Else (Inside Process Only)

process(sel, a, b) begin if sel = “00” then y <= a; elsif sel = “01” then y <= b; else y <= ‘0’; end if; end process; Use code with caution. Case Statement (Inside Process Only)

process(state) begin case state is when IDLE => output <= ‘0’; when RUN => output <= ‘1’; when others => output <= ‘0’; end case; end process; Use code with caution. Component Instantiation

To reuse an existing entity inside a new architecture, declare it as a component and map its ports.

– 1. Component Declaration (In architecture declarative region) component AndGate is port ( a : in std_logic; b : in std_logic; y : out std_logic ); end component; – 2. Component Instantiation (Between begin and end) U1: AndGate port map ( a => signal_one, b => signal_two, y => output_signal ); Use code with caution. Finite State Machines (FSM)

A clean FSM implementation uses an enumerated type and two separate processes: one for sequential state transitions and one for combinational output logic.

– State enumeration type state_type is (ST_IDLE, ST_READ, ST_WRITE); signal current_state, next_state : state_type; – State Register (Sequential) process(clk, reset) begin if reset = ‘1’ then current_state <= ST_IDLE; elsif rising_edge(clk) then current_state <= next_state; end if; end process; – Next State & Output Logic (Combinational) process(current_state, start_signal) begin – Default assignments to prevent latches next_state <= current_state; ready <= ‘0’; case current_state is when ST_IDLE => if start_signal = ‘1’ then next_state <= ST_READ; end if; when ST_READ => ready <= ‘1’; next_state <= ST_WRITE; when ST_WRITE => next_state <= ST_IDLE; end case; end process; Use code with caution. If you need to expand this cheat sheet,